The development of new generations of field effect transistors (FETs) is a driven by the reduction of the area specific on-state resistance Ron×A. Since a well-defined breakdown characteristic and a high avalanche strength are also desirable in view of reliability requirements, optimization of the transistor cell layout with respect to the breakdown characteristic is required. As an example, in dense trench transistors a narrow mesa region leads to an electrical breakdown in an area around a bottom side of the trenches. When optimizing dense trench transistors with respect to area specific on-state resistance and well-defined avalanche breakdown characteristics, a trade-off between a number of device layout parameters has to be met.
There is a need for a semiconductor device having an improved trade-off between area specific on-state resistance and avalanche strength.